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isd-300lp? low-power usb 2.0 to ata/atapi bridge ic cy7c68310 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document 38-08030 rev. *h revised june 28, 2004 1.0 features ? fixed-function mass storage device?requires no firmware code ? usb mass storage class bulk-only specification-compliant (version 1.0) ? usb 2.0-certified (tid# 40001426) ? integrated usb transceiver ? high-speed (480-mbit) and full-speed (12-mbit) support ? usb suspend/resume, remote wakeup support ? two power modes of operation?self-powered and usb bus- powered ? low power consumption allows for bus-powered opera- tion ? vbus-powered cf support ? true usb portable hdd support ? compact 80-pin tqfp packa ge with a lead-free option ? ata/atapi-6 specification-compliant?provides support for mass storage devices larger than 137gb ? 5v tolerant inputs, 3.3v output drive ? flexible usb descriptor and configuration retrieval sources ? i 2 c-compatible serial rom interface ? ata interface using vendor-specific ata command (fbh) implemented on atapi or ata device ? default on-chip rom contents for manufacturing/devel- opment ? 2-kbyte sram data buffer for ata/atapi data transfers ? ata interface supports ata pio modes 0?4, udma modes 0?4 (multiword dma not supported). ata interface operation mode is automatically selected during device initialization or manually programmed with i 2 c-compatible configuration data ? automatic detection of either master or slave ata/atapi devices ? mode page 5 support?increased support for formatting removable media devices ? ata interrupt support for atapi devices?offers more robust ata support across os platforms ? system event notification via vendor-specific ata command ? input pin for media cartridge detection or ejection request ? usb bus state indications (r eset, fs/hs mode of oper- ation, suspend/resume , bus/self-powered) ? three general purpose i/o (gpio) pins ? multiple luns supported within a single atapi device ? ata translation provides seamless ata support with standard msc drivers ? additional ata command support provided by vendor- specific atacbs (ata command blocks utilizing the msc command block wrapper) ? provisions to share ata bu s with other hosts (e.g. usb/1394 dual device) ? manufacturing interconnect test support provided with vendor-specific usb commands: ? read/write access to relevant asic pins ? manufacturing interconnect test tools ? utilizes inexpensive 30-mhz crystal for clock source. 1.1 functional block diagram cy7c68310 control logic usb ata interface logic rom 64 byte ram 2kbyte fifo usb hs/fs control logic eeprom interface control usb 2.0 xcvr 256 byte eeprom ata control 16-bit data control bulk gpio pins (3) neject a taen osc 30mhz xtal nreset sysirq diskrd y npwr500 lowpwr drvpwrvld v buspwrd v buspwrvld scl sd a v bus d- d+ figure 1-1. block diagram
cy7c68310 document 38-08030 rev. *h page 2 of 34 2.0 applications the cy7c68310 implements a usb 2.0 bridge for all ata/atapi-6 compliant mass storage devices, such as: ? hard drives, including small form factor drives (2.5?, 1.8?, and 1.0?) designed for portable consumer electronics appli- cations ? cd-rom, cd-r/w ? dvd-rom, dvd-ram, dvd-r/w ? mp3 players ? compact flash ? microdrives ? tape drives ? personal video recorders. 2.1 additional resources ? CY4617 ? cy7c68310 mass storage reference design kit ? usb specification version 2.0 ? ata attachment-6 with packet interface revision 3b ? usb mass storage class bulk-only transport specification, rev. 1.0 3.0 introduction the cy7c68310 implements a bridge between one usb port and one ata/atapi-based mass storage device port. this bridge adheres to the mass storage class bulk-only transport specification, version 1.0. the usb port of the cy7c68310 is connected to a host computer directly or via the downstream port of a usb hub. host software issues commands and data to the cy7c68310 and receives status and da ta from the cy7c68310 using standard usb protocol. the ata/atapi port of the cy7c68310 is connected to a mass storage device. a 2-kbyte buffer maximizes ata/atapi data transfer rates by minimizing lo sses due to device seek times. the ata interface supports ata pio modes 0?4, and ultra mode dma modes 0?4. the device initialization process is configurable, enabling the cy7c68310 to initialize most ata/atapi devices without software intervention. the cy7c68310 can also be configured to allow software initialization of a device if initialization requirements are not supported by cy7c68310 algorithms. 4.0 pin assignments 4.1 pin diagram figure 4-1. 80-pin tqfp cy7c68310-80ac 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 38 39 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 59 60 57 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 vdd25 vbuspwrvld vbuspwrd diskrdy sda_nimode scl npwr500 ncs1 ncs0 da2 da0 vdd33 da1 atairq ndmack atapuen iordy ndior ndiow vdd33 vdd25 dd7 tmc2 tmc1 natarst nreset lowpwr scanen gpio2_nhs gpio1 gpio0 ataen drvpwrvld sysirq neject test3 vdd33 xo xi vss vss rpu vdd25 vss rsdp dp vdd33 dm rsdm vss pvdd25 avss avss avdd25 rref avss vdd25 test0 test1 test2 vdd25 vss dmarq dd15 dd0 dd14 dd13 dd1 dd2 vdd33 dd12 vss dd11 dd3 dd10 dd4 dd6 dd8 dd9 dd5
cy7c68310 document 38-08030 rev. *h page 3 of 34 4.2 pin overview pin number pin name pin direction pin type pin description 2 rpu o usb output d+ pull-up source . power source for 1.5k pu ll-up resistor attached to d+ during full-speed operation. 5 rsdp o usb i/o usb full-speed output buffer (d+) . rsdp also functions as a current sink for termination during high-speed operation. 6 dp i/o usb i/o usb high-speed i/o buffer (d+) . 8 dm i/o usb i/o usb high-speed i/o buffer (d-) . 9 rsdm o usb i/o usb full-speed output buffer (d-) . rsdm also functions as a current sink for termination during high-speed operation. 18?20, 25 test[0:3] i 5v-tolerant input buffer active high . asic fabrication and manufacturing test mode select. these pins must be tied to gnd during normal operation. 22 xi i osc input (2.5v-tolerant) 30-mhz crystal input . 23 xo o osc output 30-mhz crystal output . 26 neject i 5v-tolerant schmitt input active low . media eject or remote wakeup requested. tie to +3.3v if functionality is not used. 27 sysirq i 5v-tolerant schmitt input active high . usb interrupt request. tie to gnd if functionality is not used. 28 drvpwrvld i 5v-tolerant schmitt input configurable polarity . device presence dete ct. this pin must not be allowed to float if functionality is not utilized. 29 ataen i 5v-tolerant schmitt input active high . ata interface enable. ?1? = normal ata operation ?0? = high-z ata interface pins and ata interface logic halted 30?32 gpio[0:1], gpio2_nhs i/o 3.3v drive, 5v-tolerant, 6-ma i ol , schmitt input general purpose i/o pins . the gpio pins must be tied to gnd if functionality is not utilized. if the hs_indicator config bit is set, the gpio2_nhs pin will reflect the operating speed of the device. ?1? = full-speed operation ?0? = high-speed operation 33 scanen i 5v tolerant input buffer active high . asic test pin. this pin must be tied to gnd during normal operation. 34 lowpwr o high-z driver, 5v-tolerant, 6-ma i ol active high . usb suspend indicator. ?0? = chip active. vbus power up to 100 ma granted. ?high-z? = chip suspend. vbus system current limited to usb suspend mode value. 35 nreset i 5v-tolerant schmitt input active low . asynchronous chip reset. 36 natarst o 3.3v drive, 5v-tolerant, 6-ma i ol active low . ata reset signal. 37, 38 tmc[1:2] i 3.3v input active high . asic test pins. these pins must be tied to gnd during normal operation. 56, 54, 52, 49,46, 44, 42, 39, 41, 43, 45, 48, 51, 53, 55, 57 dd[0:15] i/o 3.3v drive, 5v-tolerant, 6-ma i ol , schmitt input ata data signals . 58 dmarq i 5v tolerant schmitt input ata control signal . 62 ndiow o 3.3v drive, 5v-tolerant, 6-ma i ol ata control signal .
cy7c68310 document 38-08030 rev. *h page 4 of 34 63 ndior o 3.3v drive, 5v-tolerant, 6 ma i ol ata control signal . 64 iordy i 5v-tolerant schmitt input ata control signal . 65 atapuen o 3.3v drive, 5v-tolerant, 6 ma i ol ata iordy pull-up connection . for vbus-powered systems. 66 ndmack o 3.3v drive, 5v-tolerant, 6 ma i ol ata control signal . 67 atairq i 5v-tolerant schmitt input ata interrupt request . 70, 68, 71 da[0:2] o 3.3v drive, 5v-tolerant, 6 ma i ol ata address signals . 72, 73 ncs[0:1] o 3.3v drive, 5v-tolerant, 6 ma i ol ata chip select signals . 74 npwr500 o high-z driver, 5v-tolerant, 6 ma i ol active low . vbus power granted indicator. ?0? = vbus power up to bmaxpower value ?high-z? = bmaxpower value not granted (if more than 100 ma) 75 scl o high-z driver, 5v-tolerant, 6 ma i ol i 2 c-compatible clock . this pin may be left as a no-connect pin if the i 2 c-compatible interface is not utilized. 76 sda_nlmode i/o high-z driver, 5v-tolerant, 6 ma i ol , schmitt input i 2 c-compatible address/data or nimode select . 77 diskrdy i 5v-tolerant schmitt input configurable polarity . device ready. 78 vbuspwrd i 5v-tolerant schmitt input active high . bus-powered operation select pin. ?1? = bus powered ?0? = self powered 79 vbuspwrvld i 5v-tolerant schmitt input active high . indicates that vbus power is present. 1, 4, 10, 21, 47, 60 vss power digital ground . 3, 17, 40, 59, 80 vdd25 power 2.5v digital supply . 7, 24, 50, 61, 69 vdd33 power 3.3v digital supply . 11 pvdd25 power analog 2.5v supply (pll) . 12,14,16 avss power analog ground . 13 rref power pll voltage reference . current source for 2.4k (1%) resistor connected to avss. 15 avdd25 power analog 2.5v supply . 4.2 pin overview (continued) pin number pin name pin direction pin type pin description
cy7c68310 document 38-08030 rev. *h page 5 of 34 4.3 detailed pin descriptions 4.3.1 dp , dm dp and dm are the high-speed usb signaling pins, and they should be tied to the d+ and d? pins of the usb connector. because they operate at high frequencies, the usb signals require special consideration when designing the layout of the pcb. see section 15.0 fo r pcb layout guidelines. 4.3.2 rsdp , rsdm rsdp and rsdm are the full-speed usb signaling pins, and they should be tied to the dp and dm pins through 39 ? resistors. rsdp and rsdm also function as current sinks for termination during high-speed operation. 4.3.3 test[0:3] the test pins control the various test modes of the cy7c68310. most test modes are reserved for asic fabri- cation, but the following table outlines the test modes available for device manufacturing environments. the test pins must be tied to gnd for normal operation. 4.3.4 xi, xo the cy7c68310 requires a 30-mhz signal to derive internal timing. typically a 30-mhz (2.5v tolerant, parallel-resonant fundamental mode) crystal is used, but a 30-mhz (2.5v, 50% duty cycle) square wave from another source can also be used. if a crystal is used, conne ct the pins to xi and xo, and also through 20pf capacitors to gnd as shown in figure 8-1. if an alternate clock source is used, apply it to xi and leave xo open. 4.3.5 neject the neject input pin provides a means to communicate an eject button push to the ata/atapi device via event notifi- cation as well as a way to cause a usb remote-wakeup. during normal operation, asserting neject for 10ms indicates that a media eject has been requested. if the cy7c68310 is in a suspend state, and if remote wakeup is enabled by the usb host, a state change on this pin will immediately cause the cy7c68310 to perform a usb remote wakeup event. 4.3.6 sysirq the sysirq pin provides a way for systems to request service from host software by use of the usb interrupt pipe. if the cy7c68310 has no pending interrupt data to return, usb interrupt pipe data requests are naked. if pending data is available, cy7c68310 returns 16 bits of data indicating the state of the diskrdy pin, the hs_mode signal (that indicates whether cy7c68310 is operating in high-speed or full-speed), the vbuspwrd pin, the user-defined values from bits [7:3] of address 0xe of the configuration space, and the gpio pins. table 4-2 shows the bitmap for the data returned on the interrupt pipe, and the figure beneath it depicts the latching algorithm incorporated by cy7c68310. table 4-1. cy7c68310 test modes test mode description 0000 normal mode . this is the default mode of operation. 0001 reserved . 0010 limbo mode . all output pins set to high-z during limbo mode operation with the exception of the xo pin. the xo pin output cell does not have high-z control (always en abled), and must be disabled or disconnected by other means. to enter limbo mode, nreset must be t oggled after the test pins are set to ?0010?. 0011 input xnortree mode . this mode tests the connectivity of all dedi cated inputs and outputs. while in the input xnortree mode of operation, all bi-directional pins ar e wired as chain outputs. the results of the connectivity procedure will be seen on all bidirectional pins. chai n inputs (in order): vbusp wrvld, vbuspwrd, diskrdy, atairq, iordy, dmarq, nreset, ataen, drvpwrvld , sysirq, neject chain outputs (in order): gpio[2:0], dd[15:0], sda_nimode. 0100 bi-di xnortree mode . this mode test the connectivity of all bi-dir ectional inputs. while in the bi-di xnor tree mode of operation, all bi-direction al pins are wired as inputs and become part of the xnor tree chain. the results of the connectivity procedure will be seen on all output only pins . chain inputs: gpio[0], gpio[1], gpio[2], dd[7], dd[8], dd[6], dd[0], dd[5], dd[10] , dd[4], dd[11], dd[3], dd[ 12], dd[2], dd[13], dd[1] , dd[14], dd[0], dd[15], sda_nimode. chain outputs: npwr500, natarst, ndiow, ndior, ndmack, atapuen, ncs[1:0], da[2:0], lowpwr, scl 0101?1111 reserved .
cy7c68310 document 38-08030 rev. *h page 6 of 34 4.3.7 drvpwrvld drvpwrvld can be used with removable devices (such as compact flash) to indicate that the media device is present. pin polarity and function enable are controlled by bits 4 and 2, respectively, of eeprom address 0x0b. when drvpwrvld is deasserted, the cy7c68310 will remove the pull-up on d+ (causing the cy7c68310 to drop off the usb), suspend all ata state machine activity, drive all ata interface signals to ?0? (assuming ataen = ?1?), and enter into a low-power state. the cy7c68310 will remain in this state until drvpwrvld is asserted, at which time it will enable the d+ pull-up, allow resume of ata state machine activity, and begin to drive the ata interface pins (assuming ataen = ?1?). 4.3.8 ataen the ataen pin allows ata bus sharing with other host devices. deasserting ataen causes the cy7c68310 to high- z all ata bus interface pins and suspend ata state machine activity, otherwise leaving the cy7c68310 operational (usb operation continues). asserting ataen causes the cy7c68310 to reset the drive and resume normal operation. to disable usb operation and the ata interface, the drvpwrvld signal can be used in conjunction with ataen to force the cy7c68310 into a low-power state until normal operation is resumed. note that disabling the ata bus with the ataen pin during the middle of a data transfer will result in table 4-2. usb interrupt pipe data bitmap usb interrupt data byte 1 usb interrupt data byte 0 7654321076543210 0 0 0 0 0 diskrdy usb high-speed vbuspwrd user_def[4] user_def[3] user_def[2] user_def[1] user_def[0] gpio[2] gpio[1] gpio[0] figure 4-2. sysirq latching algorithm usb interrupt pipe polled? yes no nak request sysirq=1? latch state of io pins set int_data = 1 int_data = 1? no return interrupt data set int_data = 0 yes yes no yes int_data = 0 and sysirq=0? no
cy7c68310 document 38-08030 rev. *h page 7 of 34 data loss and may cause the operating system on the host computer to crash. 4.3.9 gpio pins the gpio pins allow for a general purpose input/output interface. configuration byte s 0x0e and 0x0f contain the settings for the gpio pins. see section 6.3 for details of how to use the vendor-specific co mmands to utilize the gpio functionality. the status of the gpio pins is also returned by a usb interrupt event. see sect ion 4.3.6 for sysirq details. alternatively, if the hs_indicat or config bit is set (bit 4 of eeprom address 0x0f), the gp io2_nhs pin wi ll reflect the operating speed of the device. 4.3.10 lowpwr lowpwr is an output pin th at, when in a high-z state, indicates that the cy7c68310 is in a suspend state. when lowpwr output is driven ?0 ?, the cy7c68310 is active. 4.3.11 nreset asserting nreset for a minimum of 1 ms after power rails are stable will reset the entire ch ip. an rc reset circuit should be used that ensures that no spurious resets occur. 4.3.12 atapuen this output provides contro l for the required host pull-up resistors on the ata interface. atapuen is driven ?0? when the ata bus is inactive. atapuen is driven ?1? when ata bus is active. atapuen is set to a high-z state along with all other ata interface pins when ataen is deasserted. 4.3.13 npwr500 npwr500 is an external pin that, when asserted, indicates vbus current may be drawn up to the limit specified by the bmaxpower field of the usb configuration descriptors. npwr500 will only be asserted if vbuspwrd is also asserted. if the cy7c68310 enters a low-power state, npwr500 is deasserted. when normal operation is resumed, npwr500 is restored accordingly. the npwr500 pin should never be used to control power sources for the cy7c68310. 4.3.14 scl, sda_nimode if an external eeprom device is used to store configuration information, the clock and data pins for the i 2 c-compatible port should be connecte d to the configur ation eeprom and to vcc through 2.2k ? resistors as shown in figure 8-1. if config- uration information is to be obtained from the attached ata/atapi device (imode), scl should be left as a no- connect and sda_nimode should be tied to gnd. 4.3.15 diskrdy this input pin indicates the attached device is powered and ready to begin communication with the cy7c68310. diskrdy polarity can be set using eeprom address 0x05, bit 0. diskrdy qualifies the start of the cy7c68310 initial- ization sequence. a state chang e from ?0? to ?1? on diskrdy will cause the cy7c68310 to wait for 25 ms before asserting natareset and re-initializing the device. the ata interface state machines remain inactive and all of the ata interface signals are driven logic '0' if diskrdy is not asserted (assuming ataen = '1'). diskrdy is filtered for 25 ms on the asserting edge and cleared asynchronously on the deasserting edge. 4.3.16 vbuspwrd the vbuspwrd input pin indicates whether the device will report itself as bus-powered or self-powered. vbuspwrd also qualifies the use of npwr500. based upon the state of this pin at start-up, the cy7c68310 will request the amount of current specified in the bmaxpower field of the usb configu- ration descriptor. if vbuspwrd is asserted, the cy7c68310 will report that the device is bus-powered. if vbuspwrd is deasserted, the cy7c68310 will r eport that the device is self- powered. 4.3.17 vbuspwrvld vbuspwrvld (usb vbus power valid) indicates that vbus power is present at the usb connector. vbuspwrvld qualifies driving the system?s 1.5k ? pull-up resistor on d+ (the usb specification only allows the device to source power to d+ when the host is powered). vbuspwrvld is conditioned so that it is only detected af ter valid chip configuration bits have been loaded. 5.0 functional overview 5.1 usb signaling speeds the cy7c68310 operates at two of the three signal rates that are defined in the universal serial bus specification revision 2.0: ? full-speed, with a signaling bit rate of 12 mbits/sec. ? high-speed, with a signaling bit rate of 480 mbits/sec. 5.2 ata interface the ata/atapi port on the cy7c68310 is compliant with the information technology?at attachment with packet interface?6 (ata/atapi-6) specification, t13/1410d rev 2a. the cy7c68310 supports both atapi packet commands as well as ata commands (by use of ata command blocks), as outlined in sections 5.2.1 and 5.2.2. refer to the usb mass storage class (msc) bulk only transport specification for information on command blo ck formatting. additionally, the cy7c68310 translates atapi sff-8070i commands to ata commands for seamless integration of ata devices with generic mass storage class bot drivers. the cy7c68310 also provides a vendor-specific ?event notify? ata command to automatically communicate certain usb and system events to the attached device. 5.2.1 ata command block (atacb) the ata command block (atacb) functionality provides a means of passing ata commands and ata register accesses for execution. atacb commands are transferred in the command block wrapper command block (cbwcb) portion of the command block wrapper (cbw). the atacb is distin- guished from other command blocks by the first two bytes of the command block matching the watacbsignature. only command blocks that have a valid watacbsignature are interpreted as ata command blocks. all other fields of the cbw and restrictions on the cbwcb remain as defined in the
cy7c68310 document 38-08030 rev. *h page 8 of 34 usb mass storage class bulk-only transport specification. the atacb must be 16 bytes in length. the following table and text defines the fields of the atacb. table 5-1. atacb field descriptions byte field name field description 0 bvscbsignature this field indicates to the cy7c68310 that the atacb contains a vendor- specific command block. this value of this filed must match the value in eeprom address 0x06h for this vend or-specific command to be recognized. 1 bvscbsubcommand this field must be set to 0x024h for atacb commands. 2 bmatacbactionselect this field controls the executio n of the atacb according to the bitfield values: bit 7 identifypacketdevice - this bit indicates that the data phase of the command will contain atapi (0xa1h) or ata (0xech) identify device data. setting identifypacketdevice when the data phase does not contain identify device data will result in unspecified device behavior. 0 = data phase does not contain identify device data 1= data phase contains atapi or ata identify device data bit 6 udmacommand - this bit enables supported udma device transfers. setting this bit when a non-udma capable device is attached will result in undetermined behavior. 0 = do not use udma device transfers (only use pio mode) 1= use udma device transfers bit 5 devoverride - this bit determines whether the dev bit value is taken from the cy7c68310 configuration data or from the atacb. 0 = the dev bit will be taken fr om eeprom address 0x05h, bit 5 1= the dev bit will be taken from the atacb field 0x0b, bit 4 bit 4:3 dperroroverride - these bits control the device and phase error override feature. these bits shall not be set in conjunction with bmatacbtask- fileread. 00 = data accesses are halted if a device or phase error is detected 01 = data accesses are halted if a device er ror is detected, but not a phase error 10 = data accesses are halted if a phase error is detected, but not a device error 11 = neither device or phase errors will result in halting of data accesses bit 2 pollaltstatoverride - this bit determines w hether or not the alternate status register will be polled and the bsy bit will be used to qualify the start of atacb operation. 0 = the altstat register will be poll ed until bsy=0 before proc eeding with the atacb operation 1= the atacb operation will be execut ed without polling the altstat register bit 1 deviceselectionoverride - this bit determines when the device selection will be performed in relation to the command register write accesses. 0 = device selection will be performed prior to command register write accesses 1 = device selection will be performed following command register write accesses
cy7c68310 document 38-08030 rev. *h page 9 of 34 bit 0 taskfileread - this bit determines whether or not the taskfile register data selected in bmatacbregisterselect is returned. if this bit is set, the dcbwdatatransferlength field must be set to 8. 0 = execute atacb command and data transfer (if any) 1 = only read taskfile registers selected in bmatacbregisterselect and return 0x00h for all others. the format of the 8 bytes of returned data is as follows: ? address offset 0x00 (3f6h) - alternate status ? address offset 0x01 (1f1h) - features / error ? address offset 0x02 (1f2h) - sector count ? address offset 0x03 (1f3h) - sector number ? address offset 0x04 (1f4h) - cylinder low ? address offset 0x05 (1f5h) - cylinder high ? address offset 0x06 (1f6h) - device / head ? address offset 0x07 (1f7h) - command / status 3 bmatacbregisterselect this field controls which of the taskfile register read or write accesses occur. taskfile read data will always be 8 bytes in length, and unsele cted register data will be returned as 0x00h. register accesses occur in sequential order as outlined below (0 to 7): bit 0 (3f6h) device control / alternate status bit 1 (1f1h) features / error bit 2 (1f2h) sector count bit 3 (1f3h) sector number bit 4 (1f4h) cylinder low bit 5 (1f5h) cylinder high bit 6 (1f6h) device / head bit 7 (1f7h) command / status 4 batacbtransferblockcount this value indicates the maximum requested block size in 512-byte incre- ments. this value must be set to the last value used for the ?sectors per block? in the set_multiple_mode command. legal values are 0, 1, 2, 4, 8, 16, 32, 64, and 128 where 0 indicates 256 sectors per block. a command failed status will be returned if an illegal value is used in the atacb. 5-12 batacbtaskfilewritedata these bytes contain at a register data used with ata command or pio write operations. only registers selected in bmatacbregisterselect are required to hold valid data when accessed. the registers are as follows: ? atacb address offset 0x05h (3f6h) - device control ? atacb address offset 0x06h (1f1h) - features ? atacb address offset 0x07h (1f2h) - sector count ? atacb address offset 0x08h (1f3h) - sector number ? atacb address offset 0x09h (1f4h) - cylinder low ? atacb address offset 0x0ah (1f5h) - cylinder high ? atacb address offset 0x0bh (1f6h) - device ? atacb address offset 0x0ch (1f7h) - command 13-15 reserved these bytes must be set to 0x00h for atacb commands. table 5-1. atacb field descriptions byte field name field description
cy7c68310 document 38-08030 rev. *h page 10 of 34 5.2.2 ata command block 2 (atacb2) the ata command block 2 (atacb2) functionality provides a means of passing ata commands and ata register accesses for execution. atacb2 allows for 48-bit commands. atacb2 commands are transferred in t he cbwcb portion of the cbw. the atacb2 is distinguished from other command blocks by the first two bytes of the command block matching the watacb2signature. only command blocks that have a valid watacb2signature are interpreted as atacb2 commands. all other fields of the cbw a nd restrictions on the cbwcb shall remain as defined in the usb mass storage class bulk- only transport specification. the atacb2 must be 16 bytes in length. the following table and text defines the fields of the atacb2. table 5-2. atacb2 field descriptions byte field name field description 0 bvscbsignature this field indicates to the cy 7c68310 that the atacb contains a vendor- specific command block. this value of this filed must match the value in eeprom address 0x06h for this vendor-s pecific command to be recognized. 1 bvscbsubcommand this field must be set to 0x025h for atacb2 commands. 2 bmatacb2registerselect this field controls which of the taskfile register read or write accesses occur. taskfile read data will always be 12 bytes in length, and unselected register data will be returned as 0x00h. register accesses occur in sequential order as outlined below (0 to 7): bit 0 (3f6h) - alternate status (read only, unaffected by write commands) bit 1 (1f1h) - features / error bit 2 (1f2h) - sector count bit 3 (1f3h) - lba low (sector number) bit 4 (1f4h) - lba mid (cylinder low) bit 5 (1f5h) - lba high (cylinder high) bit 6 (1f6h) - device / head (see bmatacb2actionselect1) bit 7 (1f7h) - command / status 3 bmatacb2actionselect1 this field controls the executio n of the atacb2 according to the bitfield values: bit 7 identifydevice - this bit indicates that the data phase of the command will contain atapi (0xa1h) or ata (0xech) identify device data. setting identi- fydevice when the data phase does not contain identify device data will result in undetermined device behavior. 0 = data phase does not contain identify device data 1= data phase contains atapi or ata identify device data bit 6 udmacommand - this bit enables supported udma device transfers. setting this bit when a non-udma capable device is attached will result in undetermined behavior. 0 = do not use udma device tr ansfers (only use pio mode) 1= use udma device transfers bit 5 devoverride - this bit determines whether the dev bit value is taken from the cy7c68310 configuration data or from the atacb2. 0 = the dev bit will be taken from eeprom address 0x05h, bit 5 1= the dev bit will be taken from batacb2deviceheaddata[5] bit 4 derroroverride - this bit controls the device error override feature. this bit should not be set during a bmatacb2actionselect taskfileread. 0 = data accesses are halted if a device error is detected 1 = data accesses are not halted if a device error is detected bit 3 perroroverride - this bit controls the phase error override feature. this bit should not be set during a bmatacb2actionselect taskfileread. 0 = data accesses are halted if a phase error is detected 1 = data accesses are not halted if a phase error is detected bit 2 pollaltstatoverride - this bit determines whether or not the alte rnate status register will be polled and its bsy bit will be used to qualify the start of atacb operation. 0 = the altstat register will be polle d until bsy=0 before proceeding with the atacb operation 1= the atacb operation will be executed without polling the altstat register
cy7c68310 document 38-08030 rev. *h page 11 of 34 bit 1 deviceselectionoverride - this bit determines when the device selection will be performed in relation to the command register write accesses. 0 = device selection will be performed prior to command register accesses 1 = device selection will be performed following command register accesses bit 0 ta skf il erea d - this bit determines whether or not the taskfile register data selected in bmatacb2registerselect is returned. if this bit is set, the dcbwdatatransferlength field must be set to 12. 0 = execute atacb2 command and data transfer (if any) 1 = only read taskfile registers selected in bmatacbregisterselect and return 0x00h for all others. the format of the 12 bytes of returned data is as follows: ? address offset 0x00h (3f6h) alternate status (hob=0) ? address offset 0x01h (1f6h) device / head (hob=0) ? address offset 0x02h (1f1h) error (hob=0) ? address offset 0x03h (1f2 h-m) sector count (hob=1) ? address offset 0x04h (1f3h-m) l ba low (sector number) (hob=1) ? address offset 0x05h (1f4h-m) lba mid (cylinder low) (hob=1) ? address offset 0x06h (1f5h-m) l ba high (cylinder high) (hob=1) ? address offset 0x07h (1f2h-l) sector count (hob=0) ? address offset 0x08h (1f3h-l) lba low (hob=0) ? address offset 0x09h (1f4h-l) lba mid (hob=0) ? address offset 0x0ah (1f5h-l) lba high (hob=0) ? address offset 0x0bh (1f7h) status (hob=0) 4 batacb2transferblockcount[7:4] these bits indicate the drq block size in 512-byte increments. this value is log base 2 of the block size. legal values are 0 (1 sector per block) through 8 (256 sectors per block). a command failed status will be returned if an illegal value is used in the atacb2. for commands using multiple sector pio data transfers, the number of sectors per block must equa l the current multiple sector setting of the drive. these bits should be set to ?0? for non-multiple, non-udma commands. bmatacb2actionselect2[3:0] this field controls the execut ion of the atacb according to the bitfield values: bits 3-1 reserved - these bits must be set to ?0? bit 0 48-bit-write - determines whether or not m da ta is used to read 1f2-1f5 0 = do not read or write 1f2-1f5 with ?-m? data 1 = read or write 1f2-1f5 with ?-m? data 5 batacb2deviceheaddata the contents of this field ar e used for writing the device head register when byte 2, bit 6 of the atacb2 is set to ?1?. otherwise, the value written will be determined by the bridge. bits 7-5 devhead - data used to write to device head register. bit 4 devoverride - this bit reflects the state of byte 3, bit 5 of the atacb2. bits 3-0 devhead - data used to write to device head register. 6-15 batacb2taskfilewritedata these bytes contain ata register data used with ata command or pio write operations. only registers selected in bmatacb2registerselect are required to hold valid data when accessed. the registers are as follows: ? atacb2 address offset 6h ( 1f1h ) features ? atacb2 address offset 7h ( 1f2h-m ) sector count ? atacb2 address offset 8h ( 1f3h-m ) lba low (sector number) ? atacb2 address offset 9h(1f4h-m) lba mid (cylinder low) ? atacb2 address offset ah ( 1f5h-m ) lba high (cylinder high) ? atacb2 address offset bh ( 1f2h-l ) sector count ? atacb2 address offset ch ( 1f3h-l ) lba low ? atacb2 address offset dh ( 1f4h-l ) lba mid ? atacb2 address offset eh ( 1f5h-l ) lba high ? atacb2 address offset fh ( 1f7h ) command table 5-2. atacb2 field descriptions byte field name field description
cy7c68310 document 38-08030 rev. *h page 12 of 34 5.2.3 vendor-specific event_notify command the vendor-specific event_noti fy command enables the cy7c68310 to communicate the occurrence of certain usb and system events to the attac hed device if the device?s firmware supports the event_notify command. the command code is specified by configuration address 0x02. setting this byte to 0x 00 disables the event_notify feature. the nstate0 and nstate1 values are read from the device and stored for use as the state0 and state1 values during the next execution of the event notification command. the nstate0 and nstate1 values provide temporary non-volatile storage for devices whose power is controlled by npwr500 (typically bus-powered systems) . this allows the device to store information prior to entering a usb suspend state for retrieval after resuming from t he usb suspend state. note that a usb reset from the host may interrupt the collection of data. the device must accommodate the potential for this occur- rence. the bsy and drq bits must be cleared by the device upon the completion of an event notification command. the state0 and state1 values are written with the value of nstate0 and nstate1 obtained from the previously completed event notification command. assertion of nreset resets state0 and state1 to 0x00. 6.0 configuration certain timing parameters and operational modes for the cy7c68310 are configurable. some usb configuration and descriptor values are also configurable. cy7c68310 configu- ration data should not be confus ed with the usb configuration descriptor data. 6.1 cy7c68310 configuration and usb descrip- tor sources cy7c68310 configuration and usb descriptor data can be retrieved from three sources. table 6-1 indicates the method of determining which data source is used. table 5-3. notification register read values register 7 6 5 4 3 2 1 0 error n/a sector count n/a lba low (sector number) n/a lba mid (cylinder low) nstate0 lba high (cylinder high) nstate1 device/head n/a status busy n/a n/a n/a drq n/a n/a n/a table 5-4. notification register write values register 7 6 5 4 3 2 1 0 features usb reset class specific reset usb suspend usb resume reserved reserved eject button pressed eject button released sector count reserved reserved reserved reserved self- powered bus- powered usb high-speed usb full-speed lba low (sector number) n/a lba mid (cylinder low) state0 lba high (cylinder high) state1 device/head n/a command specified in configuration byte 0x02
cy7c68310 document 38-08030 rev. *h page 13 of 34 6.1.1 i 2 c-compatible device the cy7c68310 provides support for the 24lcxxb family of eeproms. following the release of nreset, the cy7c68310 waits 50 ms and then checks for i 2 c-compatible device presence. if an i 2 c-compatible device is present but does not pass signature check, the cy7c68310 re-tests the signature with each vendor-specific usb load or read access of configuration bytes 0 and 1. once the signature check passes, i 2 c-compatible data is re turned for usb descriptor requests. if an i 2 c-compatible device is detected initially, it is always assumed present until t he next reset cycle (nreset). if an i 2 c-compatible device is present, a lack of an ack response when required causes the cy7c68310 to stall that usb request. the cy7c68310 will attempt the access again with the next usb request. 6.1.2 imode configuration and descriptor data can also be supplied by an attached mass storage device (imode) through a vendor- specific identify (fbh) at a command. the cy7c68310 provides 256 bytes of internal ram for fbh data storage. unlike operation with an external i 2 c-compatible memory device, imode operation requires the attached device first be initialized and fbh data retrieved before the cy7c68310 can allow usb enumeration. to meet usb specification require- ments, imode operation must be limited to systems that draw 100 ma or less from vbus prior to usb configuration. 6.1.3 internal rom contents the cy7c68310 also contains an internal set of cy7c68310 configuration and usb descriptors. the internal descriptors may only be used during manufacturing, as the internal rom values disable some features required for normal operation to aid use in a manufacturing environment. also, the internal rom descriptors do not provide a unique serial number (required for usb mass storage class compliance), and therefore cannot be used for shipping products. see table 6- 2 for the organization of th e internal rom contents. an external i 2 c-compatible memory device or utilization of the vendor-specific fbh identify co mmand is required to correctly configure the cy7c68310 for o peration and provide a unique serial number for msc compliance. 6.2 eeprom organization cy7c68310 configuration and usb descriptor data can be supplied from an i 2 c-compatible serial memory device. the cy7c68310 can address 2 kbytes of i 2 c-compatible data, but cy7c68310 configuration and usb descriptor information are limited to 512 bytes maximum. unused register space in the i 2 c-compatible serial memory device may be used for product specific data storage. note that no descriptor is allowed to span multiple pages within the i 2 c-compatible serial memory device. table 6-1. cy7c68310 configurat ion and usb descriptor sources sda_nimode = 0 i 2 c-compatible device present i 2 c signature check passes cy7c68310 configuration and usb descriptor retrieval method no no n/a in this mode, the cy7c68310 uses internal rom contents for usb descriptor information and configuration register values. this mode is for debug/manufacturing operation only. not for shipping products. yes n/a no in this mode, the cy7c68310 uses internal rom contents for usb descriptor information. configuration register values are loaded from internal rom. this is not a valid mode of operation. yes n/a yes the cy7c68310 retrieves all descriptor and configuration values from the vendor-specific identify (fbh) data. the cy7c68310 is configured using internal rom values until fbh data becomes available. no yes no the cy7c68310 uses internal rom contents for usb descriptor infor- mation. configuration register values are loaded from internal rom. in this mode of operation, any cy7c 68310 vendor-specific configuration access causes the cy7c68310 to recheck the signature field. once the signature check passes, srom data is returned for usb descriptors requests. this is not a valid mode of operation. no yes yes the cy7c68310 retrieves all descriptor and configuration values from the i 2 c-compatible memory device. the cy7c68310 is configured using these values.
cy7c68310 document 38-08030 rev. *h page 14 of 34 table 6-2. eeprom organization i 2 c address field name field description required i 2 c data example i 2 c data cy7c68310 configuration data 0x00 i 2 c memory device signature (lsb) lsb i 2 c memory device signature byte. 0x4b 0x01 i 2 c memory device signature (msb) msb i 2 c memory device signature byte. 0x50 0x02 event notification bits (7:0) atapi event notification command. the value of this register (if other than 0x00) is used to identify the vendor-specific event notification command (see section 5.2.3). setting this field to 0x00 disables this feature. 0x00 0x03 apm value bits (7:0) ata device automatic power management value. if an attached ata device supports apm and this field contains other than 0x00, the cy7c68310 will issue a set features command to enable apm with this register value during the drive initialization. 0x00 0x04 ata initialization timeout time in 128-mi llisecond granularity before the cy7c68310 stops polling the alt stat register for reset complete and restarts the reset proce ss (0x80 = 16.4 seconds). 0x80 0x05 usb bus mode bit (7) ? read only 0x00 usb bus mode of operation. ?0? = usb is operating in full-speed mode (12 mbit/sec) ?1? = usb is operating in high-speed mode (480 mbit/sec) atapi command block size bit (6) cbw command block size. ?0? = 12 byte atapi cb ?1? = 16 byte atapi cb master/slave selection bit (5) device number selection. this bit is valid only when ?skip ata/atapi device initialization? is active. otherwise, the value of this bit is ignored. ?0? = drive 0 (master) ?1? = drive 1 (slave) atapi reset bit (4) atapi reset during drive initialization. setting this bit causes the cy7c68310 to issue an atapi reset during device initialization. ata_natapi bit (3) ? read only. indicates if an ata or atapi device is detected. ?0? = atapi device ?1? = ata device or possible device initialization failure force usb fs bit(2) force usb full-speed only operation. setting this bit prevents the cy7c68310 from negotiating hs operation during usb reset events. ?0? = normal operation ? allow hs negotiation during usb reset
cy7c68310 document 38-08030 rev. *h page 15 of 34 ?1? = usb fs only ? do not allow hs negotiation during usb reset vs/msc soft_reset bit(1) vendor-specific/msc soft_reset control. ?0? = vendor-specific usb command utilized for soft_reset ?1? = mass storage class usb command utilized for soft_reset diskrdy polarity bit (0) diskrdy active polarity. diskrdy polarity is ignored if imode is set to ?1?. during imode operation diskrdy polarity is active high. ?0? = active high polarity ?1? = active low polarity 0x06 ata command designator value in cbw cb fi eld that designates if the cb is decoded as vendor-specific ata/cfg commands instead of the atapi command block. 0x24 0x07 reserved bits (7:1)? must be set to ?0?. 0x01 retry atapi bit (0) this bit enables the cy7c68310 to accommodate atapi devices that take longer to init ialize than what is allowed in the ata/atapi-6 specification. ?1? = retry atapi commands ?0? = normal atapi timing 0x08 initialization status bit (7) ? read only 0x00 drive initialization status. if set, indicates the drive initialization sequence state machine is active. force ata device bit (6) allows software to manually enable ata translation with devices that do not support cy 7c68310 device initialization algorithms. force ata device must be set to ?1? in conjunction with skip ata/atapi device initialization and ata translation enable. skip ata/atapi device initial- ization bit (5) forces the cy7c68310 to skip device initialization upon startup. this bit should be cleared for imode operation. the usb device driver must initia lize the attached device (if required) when this bit is set. for atapi devices, the host driver must issue an identify command utilizing ata. ?0? = normal operation ?1? = only reset the device and write the device control register prior to processing commands reserved bits (4:3) ? must be set to ?0?. last lun identifier bits (2:0) maximum number of luns device supports. 0x09 ataen bit (7) ? read only. 0x01 holds the current logic state of the ataen pin. table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 16 of 34 reserved bits (6:1) ? must be set to ?0?. srst enable bit (0) soft-reset during drive initialization. ?0? = disable soft-re set functionality ?1? = enable soft-reset during drive initialization 0x0a ata data assert bits (7:4) 0x20 ata cycle times are calculated using data assert and data recover values. standard values for ata-compliant devices and a 30.0-mhz system clock (in binary): mode 0 0101 (5+1)*33.33 = 200 ns mode 1 0011 (3+1)*33.33 = 133 ns mode 2 0011 (3+1)*33.33 = 133 ns mode 3 0010 (2+1)*33.33 = 100 ns mode 4 0010 (2+1)*33.33 = 100 ns ata data recover bits (3:0) standard recover values and cycle times for ata-compliant devices and a 30.0 mhz system clock (in binary): mode 0 1100 (4+1)+(12+1)*33.33 = 600 ns mode 1 0111 (3+1)+(7+1)*33.33 = 400 ns mode 2 0011 (2+1)+(3+1)*33.33 = 233 ns mode 3 0010 (2+1)+(2+1)*33.33 = 200 ns mode 4 0000 (2+1)+(0+1)*33.33 = 133 ns 0x0b ata data set-up bits (7:5) 0x00 set-up time is only incurred on the first data cycle of a burst. standard values for ata-compliant devices and a 30.0 mhz system clock are (in binary): mode 0 010 (2+1)*33.33 = 133 ns mode 1 001 (1+1)*33.33 = 66 ns mode 2 001 (1+1)*33.33 = 66 ns mode 3 001 (1+1)*33.33 = 66 ns mode 4 000 (0+1)*33.33 = 33 ns drive power valid polarity bit (4) controls the polarity of drvpwrvld pin. ?0? = active low (?connector ground? indication) ?1? = active high (power indication from device) override pio timing bit (3) this field is used in conjunction with ata data set-up, ata data assertion, ata data reco ver, and pio mode selection fields. ?0? = use timing information acquired from the drive ?1? = override device timing information with configuration values drive power valid enable bit (2) table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 17 of 34 enable for the drvpwrvld pin. drvpwrvld is typically only be enabled in applications where the cy7c68310 is vbus powered. ?0? = pin disabled (most systems) ?1? = pin enabled ata read kludge bit(1) pio data read high-z control. enabling this will high-z the ata data bus during pio read operations while addressing the data register. in most applications this bit is set to ?0.? ?0? = normal operation as per ata/atapi interface specifi- cation ?1? = high-z dd[15:0] duri ng pio data register reads imode bit (0) ? read only this bit reflects the state of the imode input pin at start-up. 0x0c sysirq bits(7) ? read only 0x3c this bit refl ects the current logic st ate of the sysirq input. diskrdy bit(6) ? read only this bit reflects the current logic state of the diskrdy input. ata translation enable bit(5) enable atapi to ata protocol translation enable. if enabled, and if an ata device is detected, ata translation is enabled. if skip ata/atapi device initialization is set ?1,? force ata device must also be set ?1? in order to utilize ata translation. ?0? = ata translation disabled ?1? = ata translation enable ata udma enable bit(4) enable ultra mode data transfer support for ata devices. if enabled, and the ata device reports udma support, the cy7c68310 will utilize udma data transfers. ?0? = disable ata device udma support ?1? = enable ata device udma support atapi udma enable bit(3) enable ultra mode data transf er support for atapi devices. if enabled, and the atapi device reports udma support, the cy7c68310 will utilize udma data transfers. ?0? = disable atapi device udma support ?1? = enable atapi device udma support rom udma mode bits(2:0) rom udma mode indicates the highest udma mode supported by the product. the cy7c68310 will utilize the lesser of rom udma mode and the highest mode supported by the device. udm a read operation mode timing is controlled by the device. mode 0 000 133.3 ns per 16-bit word write mode 1 001 100 ns per 16-bit word write mode 2 010 66.7 ns per 16-bit word write mode 3 011 66.7 ns per 16-bit word write mode 4 100 33.3 ns per 16-bit word write table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 18 of 34 0x0d pio mode selection bits (7:5) 0x90 pio mode selection. the pio mode reported back to the device if the override pio timi ng configuration bit is set. mode 0 000 mode 1 001 mode 2 010 mode 3 011 mode 4 100 skip pin reset bit (4) skip natarst assertion. setting this bit prevents the cy7c68310 from asserting natarst during initialization of the ata/atapi device. if this bit is set to ?1?, srst enable (address 0x09, bit 0) must also be set to ?1?. ?0? = allow natarst assertion ?1? = disable natarst assertion reserved bits (3:0) ? must be set to ?0?. 0x0e sysirq user-defined bits bits (7:3) 0x00 sysirq user_def[4:0] bits. the value of these bits will be returned to the host via the usb interrupt pipe as stated in section 4.3.6. general purpose io bits(2:0) gpio[2:0] pin values. when the gpio pins are configured as outputs, writing to these bits will set the logic value of the gpio pins to ?0? or ?1?. reading this address, regardless of whether the gpio pins are set to input or output, returns the logic value from the gpio pins. 0x0f atapi irq disable bit (7) 0x07 disables the use of the atairq signal with atapi devices. ?0? = atairq use enabled ?1? = atairq use disabled reserved bit (6) ? must be set to ?0?. int reason disable bit (5) setting to a ?1? causes cy7c68310 to ignore the contents of the interrupt reason register when talking to an atapi device. hs indicator enable bit (4) enables gpio2_nhs pin to indicate the current operating speed of the device (if output is enabled). ?0? = normal gpio operation ?1? = high-speed indicator enable reserved bit (3) ? must be set to ?1?. general purpose io pin enable bits (2:0) gpio[2:0] high-z control. these bits have precedence over bit 4 of this byte. ?0? = output enabled (gpio pin is an output). ?1? = high-z (gpio pin is an input). table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 19 of 34 usb device descriptor 0x10 blength length of device descriptor in bytes. 0x12 0x11 bdescriptor type descriptor ty pe for device descriptor. 0x01 0x12 bcdusb (lsb) usb specification release number in bcd. 0x00 0x13 bcdusb (msb) 0x02 0x14 bdeviceclass device class. 0x00 0x15 bdevicesubclass device subclass. 0x00 0x16 bdeviceprotocol device protocol. 0x00 0x17 bmaxpacketsize0 maximum usb packet size supported. 0x40 0x18 idvendor (lsb) vendor id. 0xb4 0x19 idvendor (msb) 0x04 0x1a idproduct (lsb) product id. 0x31 0x1b idproduct (msb) 0x68 0x1c bcddevice (lsb) device release nu mber in bcd lsb (product release number). 0x00 0x1d bcddevice (msb) device release number in bcd msb (silicon release number). this field entry is always returned from internal rom contents, regardless of the descriptor source. 0x01 0x1e imanufacturer index to manufacturer st ring. this entry must equal half of the address value where the string starts or 0 if the string does not exist. 0x49 0x1f iproduct index to product string. this entry must equal half of the address value where the string st arts or 0 if the string does not exist. 0x5f 0x20 iserialnumber index to serial number st ring. this entry must equal half of the address value where the string starts or 0 if the string does not exist. the usb mass storage class bulk only transport specification requires a unique serial number. 0x73 0x21 bnumconfigurations number of configurations supported. 0x01 usb device qualifier descriptor 0x22 blength length of device descriptor in bytes. 0x0a 0x23 bdescriptortype descriptor type. 0x06 0x24 bcdusb (lsb) usb specification release number in bcd. 0x00 0x25 bcdusb (msb) 0x02 0x26 bdeviceclass device class. 0x00 0x27 bdevicesubclass device subclass. 0x00 0x28 bdeviceprotocol device protocol. 0x00 0x29 bmaxpacketsize0 maximum usb packet size supported. 0x40 0x2a bnumconfigurations number of configurations supported. 0x01 0x2b breserved reserved. must be set to 0. 0x00 usb standard configuration d escriptor (vbuspwrd asserted) 0x2c blength length of configuration descriptor in bytes. 0x09 0x2d bdescriptortype descriptor type. 0x02 0x2e btotallength (lsb) number of bytes returned in this configuration. this includes the configuration descriptor plus all the interface and endpoint descriptors. 0x27 0x2f btotallength (msb) 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 20 of 34 0x30 bnuminterfaces number of interf aces supported. the cy7c68310 only supports one interface. 0x01 0x31 bconfiguration value the value to use as an argument to set configuration to select the configuration. this value must be set to 0x02. 0x02 0x32 iconfiguration index to the configurat ion string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x00 0x33 bmattributes device attributes fo r this configuration. configuration characteristics: 0x80 or 0xa0 0x34 bmaxpower maximum power consumption for this configuration. units used are ma*2 (i.e., 0x31 = 98 ma, 0xf9 = 498 ma). 0xf9 usb other speed configuration descriptor (vbuspwrd asserted) 0x35 blength length of configuration descriptor in bytes. 0x09 0x36 bdescriptortype descriptor type. 0x07 0x37 btotallength (lsb) number of bytes returned in this configuration. this includes the configuration descriptor plus all the interface and endpoint descriptors. 0x27 0x38 btotallength (msb) 0x00 0x39 bnuminterfaces number of interf aces supported. the cy7c68310 only supports one interface. 0x01 0x3a bconfigurationvalue the value to use as an argument to set configuration to select the configuration. this value must be set to 0x02. 0x02 0x3b iconfiguration index to the configurat ion string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x00 0x3c bmattributes device attributes fo r this configuration. configuration characteristics: 0x80 or 0xa0 0x3d bmaxpower maximum power consumption for this configuration. units used are ma*2 (i.e., 0x31 = 98 ma, 0xf9 = 498 ma). 0xf9 usb interface descriptor (high-speed) 0x3e blength length of interface descriptor in bytes. 0x09 0x3f bdescriptortype descriptor type. 0x04 0x40 binterfacenumber interface number. 0x00 0x41 balternatesettings alternate settings. 0x00 0x42 bnumendpoints number of endpoints. 0x03 0x43 binterfaceclass interface class. 0x08 0x44 binterfacesubclass interface subclass. 0x06 0x45 binterfaceprotocol interface protocol. 0x50 0x46 iinterface index to first interface string. this entry must equal half of the address value where the string starts or zero if the string does not exist. 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data bit description on board default 7 reserved. set to ?1? ?1? 6 self powered ?0? = bus-powered device 5 remote wake-up ?0? 4:0 reserved. set to ?0? ?0? bit description on board default 7 reserved. set to ?1? ?1? 6 self powered ?0? = bus-powered device 5 remote wake-up ?0? 4:0 reserved. set to ?0? ?0?
cy7c68310 document 38-08030 rev. *h page 21 of 34 usb bulk out endpoint (high-speed) 0x47 blength length of this descriptor in bytes. 0x07 0x48 bdescriptortype endpoint descriptor type. 0x05 0x49 bendpointaddress this is an out endpoint, endpoint number 1. 0x01 0x4a bmattributes this is a bulk endpoint. 0x02 0x4b wmaxpacketsize (lsb) max data transfer size. 0x00 0x4c wmaxpacketsize (msb) 0x02 0x4d binterval high-speed interval for polling (max nak rate). 0x01 usb bulk in endp oint (high-speed) 0x4e blength length of this descriptor in bytes. 0x07 0x4f bdescriptortype endpoint descriptor type. 0x05 0x50 bendpointaddress this is an in endpoint, endpoint number 2. 0x82 0x51 bmattributes this is a bulk endpoint. 0x02 0x52 wmaxpacketsize (lsb) max data transfer size. 0x00 0x53 wmaxpacketsize (msb) 0x02 0x54 binterval high-speed interval for polling (max nak rate). 0x01 usb interrupt endpoint (high-speed) 0x55 blength length of this descriptor in bytes. 0x07 0x56 bdescriptortype endpoint descriptor type. 0x05 0x57 bendpointaddress this is an in endpoint, endpoint number 3. 0x83 0x58 bmattributes this is an interrupt endpoint. 0x03 0x59 wmaxpacketsize (lsb) max data transfer size. 0x02 0x5a wmaxpacketsize (msb) 0x00 0x5b binterval high-speed interval for polling (max nak rate). 0x0c 0x5c reserved reserved. 0x00 usb interface descriptor (full-speed) 0x5d blength length of interface descriptor in bytes. 0x09 0x5e bdescriptortype descriptor type. 0x04 0x5f binterfacenumber interface number. 0x00 0x60 balternatesettings alternate settings 0x00 0x61 bnumendpoints number of endpoints. 0x03 0x62 binterfaceclass interface class. 0x08 0x63 binterfacesubclass interface subclass. 0x06 0x64 binterfaceprotocol interface protocol. 0x50 0x65 iinterface index to first interface string. this entry must equal half of the address value where the string starts or zero if the string does not exist. 0x00 usb bulk out endpoint (full-speed) 0x66 blength length of this descriptor in bytes. 0x07 0x67 bdescriptortype endpoint descriptor type. 0x05 0x68 bendpointaddress this is an out endpoint, endpoint number 1. 0x01 0x69 bmattributes this is a bulk endpoint. 0x02 0x6a wmaxpacketsize (lsb) max data transfer size. 0x40 0x6b wmaxpacketsize (msb) 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 22 of 34 0x6c binterval high-speed interval for polling (max nak rate). does not apply to fs bulk endpoints, set to zero. 0x00 usb bulk in endpoint (full-speed) 0x6d blength length of this descriptor in bytes. 0x07 0x6e bdescriptortype endpoint descriptor type. 0x05 0x6f bendpointaddress this is an in endpoint, endpoint number 2. 0x82 0x70 bmattributes this is a bulk endpoint. 0x02 0x71 wmaxpacketsize (lsb) max data transfer size. 0x40 0x72 wmaxpacketsize (msb) 0x00 0x73 binterval high-speed interval for polling (max nak rate). does not apply to fs bulk endpoints, set to zero. 0x00 usb interrupt endpoint (full-speed) 0x74 blength length of this descriptor in bytes. 0x07 0x75 bdescriptortype endpoint descriptor type. 0x05 0x76 bendpointaddress this is an in endpoint, endpoint number 3. 0x83 0x77 bmattributes this is an interrupt endpoint. 0x03 0x78 wmaxpacketsize (lsb) max data transfer size. 0x02 0x79 wmaxpacketsize (msb) 0x00 0x7a binterval high-speed interval for polling (max nak rate). 0xff 0x7b reserved reserved. 0x00 usb string descriptor ? index 0 (langid) 0x7c blength langid descriptor length. 0x04 0x7d bdescriptortype descriptor type. 0x03 0x7e langid (lsb) language supported (0x0409 = us english). cy7c68310 only supports one language code 0x09 0x7f langid (msb) 0x04 usb standard configuration d escriptor (vbuspwrd deasserted) 0x80 blength length of configuration descriptor in bytes. 0x09 0x81 bdescriptortype descriptor type. 0x02 0x82 btotallength (lsb) number of bytes returned in this configuration. this includes the configuration descriptor plus all the interface and endpoint descriptors. 0x27 0x83 btotallength (msb) 0x00 0x84 bnuminterfaces number of interf aces supported. the cy7c68310 only supports one interface. 0x01 0x85 bconfigurationvalue the value to use as an argument to set configuration to select the configuration. this value must be set to 0x02. 0x02 0x86 iconfiguration index to the configurat ion string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x00 0x87 bmattributes device attributes fo r this configuration. configuration characteristics: 0xc0 or 0xe0 0x88 bmaxpower maximum power consumption for this configuration. units used are ma*2 (i.e., 0x31 = 98 ma, 0xf9 = 498 ma). 0x31 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data bit description on board default 7 reserved. set to ?1? ?1? 6 self powered. ?1? = self-powered device 5 remote wake-up. ?0? 4:0 reserved. set to ?0? ?0?
cy7c68310 document 38-08030 rev. *h page 23 of 34 usb other speed configuration descriptor (vbuspwrd deasserted) 0x89 blength length of configuration descriptor in bytes. 0x09 0x8a bdescriptortype descriptor type. 0x07 0x8b btotallength (lsb) number of bytes returned in this configuration. this includes the configuration descriptor plus all the interface and endpoint descriptors. 0x27 0x8c btotallength (msb) 0x00 0x8d bnuminterfaces number of interf aces supported. the cy7c68310 only supports one interface. 0x01 0x8e bconfigurationvalue the value to use as an argument to set configuration to select the configuration. this value must be set to 0x02. 0x02 0x8f iconfiguration index to the configurat ion string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x00 0x90 bmattributes device attributes fo r this configuration. configuration characteristics: 0xc0 or 0xe0 0x91 bmaxpower maximum power consumption for this configuration. units used are ma*2 (i.e. 0x31 = 98 ma, 0xf9 = 498 ma). 0x31 usb string descriptor ? manufacturer 0x92 blength string descriptor length in bytes. 0x2c 0x93 bdescriptortype descriptor type. 0x03 0x94 bstring unicode character lsb. 0x43 (?c?) 0x95 bstring unicode character msb. 0x00 0x96 bstring unicode character lsb. 0x79 (?y?) 0x97 bstring unicode character msb. 0x00 0x98 bstring unicode character lsb. 0x70 (?p?) 0x99 bstring unicode character msb. 0x00 0x9a bstring unicode character lsb. 0x72 (?r?) 0x9b bstring unicode character msb. 0x00 0x9c bstring unicode character lsb. 0x65 (?e?) 0x9d bstring unicode character msb. 0x00 0x9e bstring unicode character lsb. 0x73 (?s?) 0x9f bstring unicode character msb. 0x00 0xa0 bstring unicode character lsb. 0x73 (?s?) 0xa1 bstring unicode character msb. 0x00 0xa2 bstring unicode character lsb. 0x20 (? ?) 0xa3 bstring unicode character msb. 0x00 0xa4 bstring unicode character lsb. 0x53 (?s?) 0xa5 bstring unicode character msb. 0x00 0xa6 bstring unicode character lsb. 0x65 (?e?) 0xa7 bstring unicode character msb. 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data bit description on board default 7 reserved. set to ?1? ?1? 6 self powered ?1? = self-powered device 5 remote wake-up ?0? 4:0 reserved. set to ?0? ?0?
cy7c68310 document 38-08030 rev. *h page 24 of 34 0xa8 bstring unicode character lsb. 0x6d (?m?) 0xa9 bstring unicode character msb. 0x00 0xaa bstring unicode character lsb. 0x69 (?i?) 0xab bstring unicode character msb. 0x00 0xac bstring unicode character lsb. 0x63 (?c?) 0xad bstring unicode character msb. 0x00 0xae bstring unicode character lsb. 0x6f (?o?) 0xaf bstring unicode character msb. 0x00 0xb0 bstring unicode character lsb. 0x6e (?n?) 0xb1 bstring unicode character msb. 0x00 0xb2 bstring unicode character lsb. 0x64 (?d?) 0x1b bstring unicode character msb. 0x00 0xb4 bstring unicode character lsb. 0x75 (?u?) 0xb5 bstring unicode character msb. 0x00 0xb6 bstring unicode character lsb. 0x63 (?c?) 0xb7 bstring unicode character msb. 0x00 0xb8 bstring unicode character lsb. 0x74 (?t?) 0x1b bstring unicode character msb. 0x00 0xba bstring unicode character lsb. 0x6f (?o?) 0xbb bstring unicode character msb. 0x00 0xbc bstring unicode character lsb. 0x72 (?r?) 0xbd bstring unicode character msb. 0x00 usb string descriptor ? product 0xbe blength string descriptor length in bytes. 0x2a 0xbf bdescriptortype descriptor type. 0x03 0xc0 bstring unicode character lsb. 0x55 (?u?) 0xc1 bstring unicode character msb. 0x00 0x1c bstring unicode character lsb. 0x53 (?s?) 0xc3 bstring unicode character msb. 0x00 0xc4 bstring unicode character lsb. 0x52 (?b?) 0xc5 bstring unicode character msb. 0x00 0xc6 bstring unicode character lsb. 0x20 (? ?) 0xc7 bstring unicode character msb. 0x00 0xc8 bstring unicode character lsb. 0x53 (?s?) 0xc9 bstring unicode character msb. 0x00 0xca bstring unicode character lsb. 0x74 (?t?) 0xcb bstring unicode character msb. 0x00 0xcc bstring unicode character lsb. 0x6f (?o?) 0xcd bstring unicode character msb. 0x00 0xce bstring unicode character lsb. 0x72 (?r?) 0xcf bstring unicode character msb. 0x00 0xd0 bstring unicode character lsb. 0x61 (?a?) 0xd1 bstring unicode character msb. 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 25 of 34 0xd2 bstring unicode character lsb. 0x67 (?g?) 0xd3 bstring unicode character msb. 0x00 0xd4 bstring unicode character lsb. 0x65 (?e?) 0xd5 bstring unicode character msb. 0x00 0xd6 bstring unicode character lsb. 0x20 (? ?) 0xd7 bstring unicode character msb. 0x00 0xd8 bstring unicode character lsb. 0x41 (?a?) 0xd9 bstring unicode character msb. 0x00 0xda bstring unicode character lsb. 0x64 (?d?) 0xdb bstring unicode character msb. 0x00 0xdc bstring unicode character lsb. 0x61 (?a?) 0xdd bstring unicode character msb. 0x00 0xde bstring unicode character lsb. 0x70 (?p?) 0xdf bstring unicode character msb. 0x00 0xe0 bstring unicode character lsb. 0x74 (?t?) 0xe1 bstring unicode character msb. 0x00 0xe2 bstring unicode character lsb. 0x65 (?e?) 0xe3 bstring unicode character msb. 0x00 0xe4 bstring unicode character lsb. 0x72 (?r?) 0xe5 bstring unicode character msb. 0x00 usb string descript or ? serial number 0xe6 blength string descriptor length in bytes. 0x1a 0xe7 bdescriptortype descriptor type. 0x03 0xe8 bstring unicode character lsb. 0xxx 0xe9 bstring unicode character msb. 0x00 0xea bstring unicode character lsb. 0xxx 0xeb bstring unicode character msb. 0x00 0xec bstring unicode character lsb. 0xxx 0xed bstring unicode character msb. 0x00 0xee bstring unicode character lsb. 0xxx 0xef bstring unicode character msb. 0x00 0xf0 bstring unicode character lsb. 0xxx 0xf1 bstring unicode character msb. 0x00 0xf2 bstring unicode character lsb. 0xxx 0xf3 bstring unicode character msb. 0x00 0xf4 bstring unicode character lsb. 0xxx 0xf5 bstring unicode character msb. 0x00 0xf6 bstring unicode character lsb. 0xxx 0xf7 bstring unicode character msb. 0x00 0xf8 bstring unicode character lsb. 0xxx 0xf9 bstring unicode character msb. 0x00 0xfa bstring unicode character lsb. 0xxx 0xfb bstring unicode character msb. 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data
cy7c68310 document 38-08030 rev. *h page 26 of 34 6.3 programming the eeprom programming of the i 2 c memory device can be accomplished using an external device progr ammer, cy7c68310 supported vendor-specific usb commands, or an in-system programmer such as a bed of nails. table 6-3 shows the format of the vendor-specific commands used to program the eeprom via usb. any vendor-specific usb write request to the serial rom device configuration space will simultaneously update internal configuration register values as well. if the i 2 c device is programmed without ven dor specific usb commands, cy7c68310 must be synchronously reset (nreset) before configuration data is reloaded. the cy7c68310 supports a subset of the ?slow mode? speci- fication (100 khz) required for 24lcxxb eeprom family device support. features such as ?multi-master,? ?clock synchronization? (the scl pi n is output only), ?10-bit addressing,? and ?cbus device support? are not supported. vendor-specific usb commands allow the cy7c68310 to address up to 2 kbytes of data (although configu- ration/descriptor information is limited to 512 bytes of register space). 6.3.1 load_config_data this request enables configur ation data writes to the data source specified by the wvalue field. the windex field specifies the starting address and the wlength field denotes the data length in bytes. legal values for wvalue are as follows: ? 0x0000 configuration bytes, address range 0x2 ? 0xf ? 0x0002 external i 2 c memory device. configuration byte writes must be constrained to addresses 0x2 through 0xf, as shown in table 6-2 . attempts to write outside this address space will result in a stall condition. configuration byte writes on ly overwrite cy7c68310 configu- ration byte registers, the original data source remains unchanged (i 2 c-compatible memory device, fbh identify data, or internal rom). single byte writes to the i 2 c-compatible memory devices can start at any address. writes gr eater then a single byte must only start on eight-byte boundaries, meaning that the address value must be evenly divisible by eight. writes to i 2 c- compatible memory devices must not cross 256-byte page boundaries, i.e., start and finish write addresses must have equal modulo 256 values. write operations with beginning and end addresses that do not fall in the same 256-byte page will result in a stall condition. illegal values for wvalue as well as attempts to write to an i 2 c-compatible memory device when none is connected will result in a stall condition. 6.3.2 read_config_data this usb request allows data retrieval from the data source specified by the wvalue field. data is retrieved beginning at the address specified by the wind ex field. the wlength field denotes the length in bytes of data requested from the data source. legal values for wvalue are as follows: ? 0x0000 configuration bytes, addresses 0x0 ? 0xf only ? 0x0001 internal rom ? 0x0002 external i 2 c-compatible memory device ? 0x0003 vendor-specific identify (fbh) data illegal values for wvalue will result in a stall condition on the usb port. attempted reads from an i 2 c-compatible memory device when none is connected or attempted reads from fbh data when not in imode will result in a stall condition. attempts to read configuration bytes with starting addresses greater than 0xf will also result in a stall condition. 0xfc bstring unicode character lsb. 0xxx 0xfd bstring unicode character msb. 0x00 0xfe bstring unicode character lsb. 0xxx 0xff bstring unicode character msb. 0x00 table 6-2. eeprom organization (continued) i 2 c address field name field description required i 2 c data example i 2 c data table 6-3. eeprom-related vendor-speci fic commands label bmrequesttype brequest wvalue windex wlength data load_config_data 0x40 0x01 data destination starting address data length configuration data read_config_data 0xc0 0x02 data source starting address data length configuration data
cy7c68310 document 38-08030 rev. *h page 27 of 34 7.0 timing characteristics 7.1 i 2 c-compatible memory device interface timing 7.2 usb interface timing the cy7c68310 transceiver complies to the timing character- istics as stated in the usb s pecification version 2.0. the cy7c68310 can operate at either the high-speed or full-speed signalling rate. 7.3 ata/atapi interface timing the ata interface supports at a pio modes 0 to 4, and ultra dma modes 0 to 4, per the ata attachment ? 6 with packet interface revision 3b. all input signals on the ata/atapi port are considered asynchronous and are synchronized to the chip's internal system clock. all output signals are clocked using the chip?s internal system clock, for which there is no external reference. thus, the output signals should also be considered asynchronous. the pio mode used for data register accesses is retrieved from the device or specified in the cy7c68310 configuration bytes. 7.4 external clock source timing the cy7c68310 derives its internal system clock from an external clock source. the external clock input signal frequency is measured at one half of the 2.5v power source (vdd25). the cy7c68310 internal pll can be clocked using either a 30-mhz (0.005%) fundamental-mode crystal or a 2.5v, 50% duty-cycle square wave. the recommended external clock source for the cy7c68310 is the pre xh30prf10bl crystal (10-pf load capacitance). 7.5 reset timing the cy7c68310 requires an off-chip power-on reset circuit. nreset must be held asserted for a minimum of 1 ms after power is stable to cause a chip reset. 8.0 external circuitry requirements certain external components are required for proper cy7c68310 operation. the following figure details the minimum required circuitry for normal operation. additional components may be required to support configurable cy7c68310 features, if utilized. i 2 c-compatible device parameter symbol value clock high time t high 5066 ns clock low time t low 5066 ns start condition hold time t hd:sta 5066 ns start condition set-up time t su:sta 5066 ns data output hold time t hd:dat 5066 ns data output set-up time t su:dat 5066 ns stop condition set-up time t su:sto 5066 ns required data valid before clock t dsu 500 ns min time bus must be free before next transmission t buf 5066 ns figure 7-1. i 2 c interface timing t low t high t hd:sta t su:sta t hd:dat t su:dat t dsu scl sda out sda in t buf t su:sto
cy7c68310 document 38-08030 rev. *h page 28 of 34 8.1 ata interface termination design practices as outlined in the ata/atapi-6 specification for signal integrity should be followed with systems that utilize a ribbon cable interconnect between the cy7c68310?s ata interface and the attached ata/atapi device, especially if ultra dma mode is utilized. 8.2 power supply regulation at no time should the 3.3v power rail drop below the 2.5v rail for proper device operation. care should be taken to ensure that the power rails rise and fall without allowing the 3.3v supply to drop below the 2.5v supply. the recommended method is to cascade voltage regulating circui ts such that the 2.5v supply is powered from the 3.3v supply. 8.3 pull-ups/pull-downs on high-z pins certain output pins act as open-drain and remain at a high-z state unless asserting a ?0.? these pins include scl, sda, lowpwr, and npwr500. if their functionality is utilized, these pins must be tied to pull-up resistors to avoid floating while in a high-z state. these pi ns can be left as no-connects if the functionality is not utilized. 9.0 manufacturing interconnect test sup- port manufacturing test mode is pr ovided as a means to implement board- and system-level interconnect tests. during manufac- turing test mode operation, a ll outputs not associated directly with usb operation are controllable. normal state machine and register control of output pins are disabled. two vendor- specific usb requests (load_mfg_data and read_mfg_data) are used in manufacturing test mode operation. 9.1 load_mfg_data this usb request is used to ena ble and control manufacturing test mode operation. while in manufacturing test mode, individual pins may be asserted or deasserted depending upon the contents of the data fiel d. the dd and gpio pins may also be set to a high-z state in preparation for read_mfg_data command operations. control of the select cy7c68310 i/o pins and their high-z controls are mapped to the usb data packet associated with this request. legal values for wvalue are as follows: ? 0x0000 normal operation mode ? returns cy7c68310 to normal operation regardless of previous command data sets (power-on reset default). ? 0x0001 manufacturing test mode ? manufacturing test registers control spec ific cy7c68310 outputs cells to enable board leve l testing in the manufac- turing environment. legal values for wlength are as follows: ? 0x0000 valid only when wvalue = 0x0000; used when disabling manufacturing test mode of operation ? 0x0007 valid only when wvalue = 0x0001. for proper manufacturing test mode o peration, wlength must equal 0x0007. any data packet lengths greater than 7 will result in a stall condition. 30mhz 9pf 9pf 1.5k ? cy7c68310 xo xi dm rpu 39 ? 39 ? d+ d- sda 1.5k ? 3.3v scl 3.3v 100 ? rref avss 2.4k ? (1%) rsdm 1.5k ? dp rsdp scanen tmc[1:2] vbuspwrvld vbus 62k ? 0.1 f 39k ? figure 8-1. external circuitry requirements table 9-1. load_mfg_data command format label bmrequesttype brequest wvalue windex wlength data load_mfg_data 0x40 0x05 disable/enable start ing address data length mfg. test data
cy7c68310 document 38-08030 rev. *h page 29 of 34 9.2 read_mfg_data this usb request returns a ?snapshot in time? of selected input pins. the input pin states are bit-wise mapped to the usb data packed associated with this request. cy7c68310 input pins not associated directly with usb operation can be sampled at any time during normal or manufacturing test mode operation. this request is independent of normal cy7c68310 state machine control or manufacturi ng test mode write operations. legal values for wvalue are as follows: ?0x0000wvalue must be set to 0x0000. legal values for wlength are as follows: ? 0x0001?0x0008 any wlength value greater than 0x0008 will result in a stall response. table 9-2. bit-wise mapping of load_mfg_data test data byte bit(s) test/high-z control register name 00 lowpwr 0 1 reserved ? value will not affect output 0 2 npwr500 03 natarst 0 4 ndiow 0 5 ndior 06 ndmack 0 7 atapuen 1 0 reserved ? value will not affect output 1 2:1 ncs[1:0] 1 5:3 da[2:0] 16 scl 1 7 dd_en ? ?1? = enable output (set for writ es), ?0? = high-z dd[15:0] (set for reads) 2 7:0 dd[7:0] 3 7:0 dd[15:8] 4 2:0 gpio[2:0] 4 3 reserved ? value will not affect output 4 6:4 gpio_en[2:0] ? ?1? = enable output (set for wr ites), ?1? = high-z gpio[2:0] (set for reads) 4 7 reserved ? value will not affect output 5 7:0 reserved ? value will not affect output table 9-3. read_mfg_ data command format label bmrequesttype brequest wvalue windex wlength data read_mfg_data 0xc0 0x06 0x00 0x00 data length mfg. test data
cy7c68310 document 38-08030 rev. *h page 30 of 34 10.0 absolute maximum ratings storage temperature ............................................................................................................ .............. .............. ........ ?65 to 150c ambient temperature with power supplied ................ ........................................................................ ............................. 0 to 70c supply voltage to ground potential . ............ .............. .............. .............. .............. .............. .......... ..............................?0.5 to 5.5 v dc input voltage to any input pin .............................................................................................. ...............................?0.5 to 5.5 v dc voltage applied to outputs in high-z ........................................................................................ ...........................?0.5 to 5.5 v power dissipation ........................................... ................................................................... ...............................................235 mw static discharge voltage (meets nec asic esd specifications iec-gq-6002-01 and iec-6005-01) .. ............. ............> 2000 v max output current per i/o port . ............................................................................................... ..........................................20 ma latch-up current ............................................................................................................... ..............................................> 200 ma table 9-4. bit-wise mapping of read_mfg_data test data byte bit(s) pin name 00drvpwrvld 0 1 vbuspwrvld 0 2 vbuspwrd 03diskrdy 0 4 sysirq 0 5 iordy 06dmarq 0 7 neject 10atairq 1 1 will always return ?1? 12lowpwr 1 3 reserved ? disregard value 14npwr500 1 5 natarst 16ndiow 17ndior 20ndmack 2 1 atapuen 2 2 reserved ? disregard value 2 4:3 ncs[1:0] 2 7:5 da[2:0] 3 7:0 dd[7:0] 4 7:0 dd[15:8] 5 2:0 gpio[2:0] 5 3 will always return ?0? 54dd_en 5 7:5 gpio_en[2:0] 6 0 mfg_sel (manufacturing test mode enable) 61ataen 6 2:7 will always return ?1? 7 7:0 will always return ?1?
cy7c68310 document 38-08030 rev. *h page 31 of 34 11.0 operating conditions operating temperature.......................................................................................................... .......................................... 0 to 70c 12.0 dc characteristics 13.0 ordering information parameter description min. typ. max. unit v dd digital voltage supply 2.25 2.50 2.75 v v dda analog voltage supply 2.25 2.50 2.75 v v ddio i/o cell voltage supply 3.0 3.3 3.6 v v ih input high voltage 2.0 v ddio + 0.5 v v il input low voltage ?0.5 0.8 v v oh output high voltage at i oh 2.4 v v ol output low voltage at i ol 0.4 v i oh source current at v oh 6ma i ol sink current at v ol 6ma i ncfg unconfigured current full-speed 40 ma high-speed 60 ma i cc configured idle full-speed 2.5v supply 36 ma 3.3v supply 2 ma high-speed 2.5v supply 55 ma 3.3v supply 2 ma configured operational full-speed 2.5v supply 53 ma 3.3v supply 11 ma high-speed compact flash 2.5v supply 65 ma 3.3v supply 6 ma 2.5? hdd (see note) 2.5v supply 73 ma 3.3v supply 9 ma 3.5? hdd (see note) 2.5v supply 74 ma 3.3v supply 19 ma i sup current in usb suspend (inactive, connected) 250 a i slp current in sleep mode (inactive, unconnected) 0.7 10 a note: all values in this table assume 25 c ambient temperature and nominal voltage unless otherwise stated. all ?configured oper- ational? measurements assume a 50/50 read/write duty cycle. part number [package type cy7c68310-80ac 80-lead tqfp cy7c68310-80axc [1] 80-lead tqfp lead-free package CY4617 cy7c68310 mass storage reference design kit note: 1. the lead-free option should be used for new designs. it is re commended that existing designs migrate to lead-free parts.
cy7c68310 document 38-08030 rev. *h page 32 of 34 14.0 package diagram 15.0 pcb layout recommendations the cy7c68310 contains high-speed analog circuitry that is sensitive to system noise. in particular, noise on both analog and digital power supplies must be minimized to ensure reliable, high-performance oper ation. special attention should also be given to the design of the frequency generation, voltage reference, and usb interface circuits. cypress recom- mends using the following guidelines in designing any product that uses the cy7c68310. ? the 3.3v power rail must remain above the 2.5v rail at all times for proper device operation. ? dp and dm trace lengths should be kept to within 2 mm of each other and must not exceed 37 mm in total length, with a preferred length of 20?30 mm. ? maintain a solid ground plane under the dp and dm traces. do not allow the plane to be split under these traces. ? do not place vias on the dp or dm traces. ? isolate the dp and dm traces from all other signal traces by no less than 10 mm. ? the dp and dm common mode trace impedance should be controlled to 45 ? with total differential impedance controlled to 90 ? (10%). ? the vdd power plane should be as solid as possible with direct paths from the voltage regulator to all discrete com- ponents. a four layer board is required with inner layers dedicated to power and ground planes. digital ground should cover one entire layer of the design. ? analog and digital power planes must be isolated using in- ductors. ? ceramic or tantalum capacitors are required. do not use electrolytic capacitors. electrolytic capacitors have higher lead inductance and series resistance values that have been observed to contribute to increased power supply noise. ? adequate bypass capacitance must be implemented very near to the cy7c68310 power pins. one ceramic bypass capacitor per power/ground pair is recommended. ? all termination and pull-up resistors (including dp and dm) should be placed within 5 mm of the cy7c68310 pins. ? the crystal and rref external resistor components sh ould be placed as near the cy7c68310 pins as possible. figure 14-1. 80-pin tqfp package diagram 80-lead thin plastic quad flat pack (12 x 12 x 1.0 mm) a8012x12 51-85175-**
cy7c68310 document 38-08030 rev. *h page 33 of 34 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 16.0 disclaimers, trademarks, and copyrights purchase of i 2 c components from cypress, or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided t hat the system conforms to the i 2 c standard specification as defined by philips. isd-300lp is a trademark of cypress se miconductor. all product and company names mentioned in this document are the trademarks of their respective holders.
cy7c68310 document 38-08030 rev. *h page 34 of 34 document history page description title: cy7c68310 isd-300lp? lo w-power usb 2.0 to ata/atapi bridge ic document number: 38-08030 rev. ecn no. issue date orig. of change description of change ** 118297 09/18/02 bha new data sheet *a 120307 12/12/02 gir revised for preliminary status *b 123509 04/04/03 gir revised to include first silicon information *c 126049 04/07/03 cvr post to exte rnal website cy7c68310-80ac *d 126323 05/21/03 gir updated suspend current and included sleep mode in section 12.0 added esd testing methodology and power dissipation values to section 10.0 revised for final status *e 127185 06/05/03 beh changed static discharge voltage to > 2000v(1) replaced previous status discharge f ootnotes with the following: ?1. meets nec asic esd specifications iec-gq-6002-01 and iec-6005-01? changed dc specification i slp <10 ua typical to 10 ua max *f 127739 09/03/03 gir corrected formatting of all tables added sections on atacb and atacb2 corrected pin descriptions in sections 4.3. 4, 4.3.6, 4.3.8, 4.3. 15, 4.3.16, and 4.3.17 corrected values/contents of some eeprom table fields to clarify iros contents divided 2.5v and 3.3v current consumption in section 10 swapped order of pcb layout guidelines and package diagram sections corrected spelling and grammar added usb certification logo to cover page added usb-if test id number to section 1.1 list *g 131946 02/06/04 kku updated to include lead-free part numbers. section 1.1 changed ?compact 80-lead tq fp? to ?compact 80-pin tqfp package with a lead-free option? section 11.0 added: cy7c68310-80azc 80-lead tqfp lead-free package with footnote that new designs sh ould use lead-free part and existing designs should migrate to lead-free parts. *h 234589 see ecn kku reformatted data sheet to new standard. changed section 12.0 for lead free marketi ng part number in accordance to spec change in 28-00054.

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